Nonlinear Adaptive Filtering for MIMO Multi-Antenna Wireless Communications


Professor Sun-Yuan Kung
Email: kung@ee.princeton.edu
Abstract of talk
Friday, September 6, 14:00-18:00

Fields of Research Activity: VLSI signal processing, array processors, neural computing, digital signal processing, application-driven total system.

Experience: One year of industrial experience in LSI circuit design; fourteen years of teaching and research at the University of Southern California and Princeton University. He has taught courses in linear algebra, signal processing, spectrum analysis, linear systems, neural computing, and VLSI array processors. He has authored two textbooks and more than two hundred technical papers.

Biography: Sun-Yuan Kung was born in Taiwan on January 2, 1950. He received the B.S. in Electrical Engineering from the National Taiwan University in 1971; M.S. in Electrical Engineering from the University of Rochester in 1974; and Ph.D. in Electrical Engineering from Stanford University in 1977.
From 1977 to 1987, he was on the faculty of Electrical Engineering-Systems at the University of Southern California. In 1984, he was a Visiting Professor at Stanford University and later in the same year, a visiting professor at the Delft University of Technology. Since September 1987, he has been a Professor in the Department of Electrical Engineering, Princeton University. He currently serves on the IEEE Technical Committees on VLSI Signal Processing and Neural Networks and an Editor-in-Chief of Journal of VLSI Signal Processing. Membership in Societies: IEEE (Fellow), ACM (Member).

Typical Publications:

  1. ``VLSI Arrays Processors,'' Prentice-Hall, Inc., 1988 (translated into Russian, Chinese).
  2. ``VLSI and Modern Signal Processing,'' (co-editor, with H.J. Whitehouse and T. Kailath), Prentice-Hall, 1985 (translated into Russian).
  3. ``Optimal Hankel-Norm Model Reduction-Multivariable Systems,'' (with D. Lin), IEEE Transactions on Automatic Control , vol. AC-26, pp. 832-852, Aug. 1981.
  4. ``On Supercomputing with Systolic/Wavefront Array Processors,'' Proceedings IEEE , vol. 72, No. 7, pp. 876-884, July 1984.
  5. ``Wavefront Array Processors-Concept to Implementation,'' (with S.C. Lo, S.N. Jean and J.N. Hwang), Computer Society of the IEEE, Vol. 20, No. 7, pp. 18-33, July 1987.
  6. ``Fault-Tolerant Array Processors Using Single-Track Switches,'' (with S.N. Jean and C.W. Chang), IEEE Transactions on Computers , Vol. 38, No. 4, pp. 501-514, April 1989.
  7. ``Neural Network Architectures for Robotic Applications,'' (with J.N. Hwang), IEEE Trans. on Robotics and Automation , Vol. 5, No. 5, pp. 641-657, Oct. 1989.
  8. ``Systolic Architectures and Implementation Cosndierations for Hidden Markov Models,'' (with J.N. Hwang and J. Vlontzos), IEEE Trans. on Acoustics, Speech, and Signal Processing , Vol. 37, No. 12, pp. 1967-1979, Dec. 1989.
  9. ``Systolic Architectures for Kalman Filtering,'' (with J.N. Hwang), IEEE Trans. on Acoustics, Speech and Signal Processing , Vol. 39, No. 1, pp. 171-182, Jan. 1991.
  10. ``Digital Neural Networks,'' Prentice-Hall, Inc. Spring 1993.